Dynamic Reconfiguration of an Application on Hybrid Reconfigurable Systems

A formal methodology for automatic hardwaresoftware partitioning and co-scheduling the tasks of an application between Microprocessor and Programmable Logic Devices (PLDs) has become emerging research area of hardware software co-design. The main objective of this research is to get full advantage of hardware utilization and speedup the application execution. Hardware software partitioning and scheduling the tasks of an application on Hybrid Reconfigurable Systems (HRS) became a critical issue for efficient hardware resource utilization and speedup the application execution. The main objective of this paper is, partition the application into software, hardware and hybrid tasks by considering some predefined parameters of tasks of the application, reconfigurable logic unit array and schedule them onto HRS. In this research, the HRS is combination of Microprocessor (μP) and array of Reconfigurable Logic Devices like Field Programmable Gate Arrays (FPGAs) with variable area reconfigurable logic units (RLUs). In this research, Algorithms for Partition and schedule the tasks of an application onto HRS would be implemented and verified them by using SystemC environment to support hardware software co-design. Index Terms Dynamic Reconfiguration, Hybrid Reconfigurable Systems, Field Programmable Systems, Microprocessor, Reconfigurable Logic Unit.